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AMD Preps for Hammer, Opens Developer Center

In a little ribbon cutting ceremony, chipmaker Advanced Micro Devices (AMD) Tuesday opened the doors to its new AMD Developer Center and inched closer to the release of its Hammer technology.

Located at the company's Sunnyvale, Calif., headquarters, the facility is designed to help commercial software and hardware developers think of new ways to use AMD chips for products based on its Hammer technology. Developers can schedule consultations with AMD 64-bit code experts, either online or in person.

The new Opteron chips based on Hammer technology, due out in March or April, are expected to debut in several servers with a notebook version of the chips coming out about the same time.

In concert with the Development Center, AMD also released two additional development support resources - a SuSE Linux beta x86-64 distribution to more than 150 AMD partners currently working with AMD Opteron processor-based development platforms and the AMD x86-64 Architecture Programmer's Manual. The five-volume guide can either be ordered in hard copy or downloaded as a PDF.

AMD said the fact that it is making SuSE's x86-64 Linux distribution available now is no coincidence. The company said the beta release was expected to coincide with the first shipments of AMD Athlon processors based on Hammer technology.

"With formal development resources in place, AMD's software and hardware partners are empowered to create 32-bit and 64-bit applications and drivers for the x86-64 platform," said AMD vice president of Platform Engineering and Infrastructure, Computation Products Group Richard Heye.

Unlike Intel's start-from-scratch, 64-bit Itanium, AMD insists Hammer will let IT managers move to 64-bit software while preserving their investment in 32-bit applications. Its X86-64 technology builds on, instead of replacing, the familiar X86 instruction set, while addressing huge amounts of physical and virtual memory (thanks to 40- and 48-bit address spaces, respectively) and providing native 64-bit integer and address register files and data paths.

The Hammer architecture combines an eighth-generation, 0.13-micron-process core with integrated Northbridge; a DDR memory controller to significantly reduce DRAM latency; separate Level 1 instruction and data caches; a Level 2 cache; and HyperTransport input/output technology for high-bandwidth, chip-to-chip communication and support for glueless multiprocessing.

The "ClawHammer" CPUs are expected to support 1- and 2-way desktop, workstation, and midrange server platforms, while their "SledgeHammer" cousins will scale to 4- and 8-way multiprocessing. AMD promises that 4-way systems will be able to achieve up to 8GB/sec of aggregate memory copy bandwidth, compared to today's fastest bus-based systems' 3.2GB/sec theoretical and 2.1GB/sec real-world bandwidth, while 8-way systems will address up to 64 DIMMs or 128GB of physical memory, with four HyperTransport links providing I/O capacity up to 25GB/sec.

To help spread the word about its Hammer technology, AMD is launching a 20-city U.S. tour, entitled "AMD Reality Check: Extreme Performance Project 2." Starting in San Diego, Calif., the tour will caravan across the country with stops in major metropolitan areas to share information and connect with PC enthusiasts, system builders and retail partners.