RealTime IT News

Intel Powers Down its Chips

SAN FRANCISCO -- Never one to sit still with its chip technology, Intel Monday said it would unveil several advancements to its multiprocessors and other circuits.

Appearing before the IEEE International Solid-State Circuits Conference this week, the chip making giant is expected to submit 12 separate papers to the standards body outlining what it has accomplished with various technologies including a 5GHz Floating Point Multiply-Accumulator (MAC), new "Sleep" Transistors, an improved Multiphase Clock Generator and a 1.5GHz third-generation Itanium Processor.

The Santa Clara, Calif.-based company says all of the advancements are designed to reduce the amount of power both in delivery and dissipation.

"There is no one single bullet to power and leakage," said Intel Fellow Shekhar Borkar. The old adage of 'performance at any cost' is history. The new mantra is 'valued performance at lower cost -- and power. One of the things we're doing to address this is looking at our transistor architectures."

In the next three days, Intel said it would submit the following papers:

  • 8Gb/s Differential Simultaneous Bidirectional Link with 4mV 9ps Wavefront Capture Diagnostic Capability
  • Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors.
  • A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-performance Microprocessors
  • A 1.6Gb/s/pair Electromagnetically Coupled Multidrop Bus Using Modulated Signaling
  • A 1.5GHz Third Generation Itanium Processor
  • A 10GHz TCP Offload Accelerator for 10Gb/s Ethernet in 90nm Dual-V CMOS
  • A 1.8 128Mb 125MHz Multi-level Cell Flash Memory with Flexible Read While Write
  • A 5GHz Floating Point Multiply-Accumulator in 90nm Dual V CMOS
  • A 400MT/s 6.4GB/s Multiprocessor Bus Interface
  • Scalable Sub-10ps Skew Global Clock Distribution for a 90nm Multi-GHz IA Microprocessor
  • Cascaded PLL Design for a 90nm CMOS High-Performance Microprocessor
  • A Replica-Biased 50% Duty Cycle PLL Architecture with 1x VCO

Of certain interest to manufacturers is the 5GHz Floating Point MAC specification, which Intel says the special purpose hardware could be applied to any of Intel's brands including Pentium, XScale and its new Centrino line, expected to debut on March 12.

Based on Novel Algorithm, the device is a carry-save, single-cycle accumulate floating-point unit, with a 12-stage pipeline and based on 90nm process technology. Intel said at room temperature, the MAC could produce sustained 5 gigaflops-per-second performance while only sucking up 1.2 Watts of power.

"This is not a stand alone chip, but built into our future processors," said Borkar. "Today's floating points are very flexible, but they are not optimized and take more power."

Pushing the envelope further, Intel said its improvements in "Sleep" Transistors have shown less power leakage in individual circuits than previous designs.

"Using last year's technique, we were saving 9.6 percent of power. Now we are saving 10.3 percent with overhead," said Borkar.

From a larger perspective, Borkar said a laptop using its new transistors could be saving between 10 and 20 percent more in battery power.

Madison Advancements Delay Montecito Release
Intel is also filling in the gaps of its 64-bit Itanium processor lineup by including a third-generation to its server processor.

The company said it is on track to release three separate 1.5 GHz Madison chips, built with the 130nm process with L3 cache sizes of 3-, 4-, and 6MB.

"This is basically a drop-in replacement to our 1GHz McKinley line," said Intel Enterprise Processor Division general manager Nimish Modi. "We are putting bigger amounts on die and expanding the cache. We can get 30 to 50 percent better performance on the same circuit and now we can tack on more transistors and squeeze out more performance."

The fourth generation of Itanium chips (due out in 2004) includes another Madison with up to 9MB L3 cache. Intel expects the processor to reach speeds over 1.5 GHz with more than 500 transistors. The company is also looking at unveiling its lower-power version of Madison for rack-mounted systems -- codenamed Deerfield -- about the same time.

But, the insertion of a third and fourth generation Itanium Madison delays Intel's 90nm Montecito processor by a year. Originally due out in 2004, Intel said it decided to make the fifth-generation Itanium a dual-core processor with each core having its own L3 cache.

"The trade off is that unified cache is too complex of a design. Dual-core offered us better performance and we wanted to focus on time to market," said Modi.

Intel said the 2005 rollout for Montecito still keeps it inline for the company's goal of implemented a new technology every two years. The company expects its Pentiums will debut the latest 90nm process later this year with 65nm process technology appearing in 2005.

Modi said Intel's latest craze of Hyper-Threading its chips would make its way into the Itanium family, but the company declined to say which processor it would rest on.