RealTime IT News

Future Chips to Reflect 'Era of Tera'

SAN FRANCISCO -- Intel is rethinking its nearly 25-year-old chip architecture to address a growing need for faster and more powerful processing.

CTO Pat Gelsinger on Thursday said the Santa Clara, Calif., chip making giant is already preparing for the "era of tera-scale" computing.

"We're at the tip of the iceberg in terms of the digitization of information," Gelsinger said at the company's bi-annual technology showcase here. "Processors will need to handle terabytes of data and deliver terabits per second of bandwidth. There needs to be an architectural paradigm shift. We cannot do what we did in the 80s by borrowing our designs from the mainframes."

Instead, Intel's research and development is taking its cue from high-performance computing (HPC) systems that only use the resources they need. Based on papers the company presented at the ISSCC conference earlier this week, Intel's future processors will not be defined by frequency, as much as by how architecturally efficient they are.

"The dirty little secret of the industry is that most of the time spent on these big machines is waiting for the memory to load," Gelsinger said. "If we look on this progression of technological advances, the underlying steps have not always been smooth. There are some great challenges such as heat problems, memory latency and interconnect delays."

Intel sees increased demand on systems, especially in the multi-billion-dollar digital imaging sector, which is already approaching exabyte levels of computational needs. Intel is working on improving its chips to address image recognition, mining and synthesis.

"We realize that these workloads are a convergence driving architectural needs," Gelsinger said.

Intel's Hyper Threading technology, which partitioned applications at the processor level, was only a "baby step", according to Gelsinger. He conceded that Intel is only at the beginning of developing its next-generation threading designs; projecting solutions by the end of 2010. The CTO added that future Intel chips would be built with massive multi-cores and new chip constructs would need a redesign of the interconnect as well.

"Our Achilles heel has been programmability. That thinking that there is a layer beyond Moore's Law ," Gelsinger said.

To make its future designs scalable, Intel is also working on "helper-threading," a technology that pre-warms caches and executes parallel tasks on a single processor. Gelsinger said Intel is working on a prototype and running research for a future release of its Itanium processor. As in the past, Intel is expected to create reference platforms to universities for testing and research.

Intel also is researching new technologies to make these new architectures more adaptable to multiple environments, applications and users. For example, Gelsinger described how Intel researchers are developing a reconfigurable radio architecture for future chips to enable devices to communicate over various networks, whether it be 802.11a, b or g, Bluetooth or other wireless technologies.