Broadcom: Chip on its Shoulder
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Broadcom, which provides integrated circuits enabling broadband communications, announced a 10-Gigabit per second (Gbps) Dense Wavelength Division Multiplexing (DWDM) Transport Processor.
The device will alleviate the space and power constraints urgently needed in service providers' central offices by enabling the development of compact, low power DWDM equipment that increases the number of wavelengths to over 200 on an existing, single strand of fiber, officials said.
The Broadcom BCM8511 Transport Processor integrates a digital wrapper, Forward Error Correction (FEC), and a SONET/SDH framer with performance monitoring logic and a serial 10 Gbps transceiver into a single chip. This unprecedented level of integration results in one-third the power and one-quarter the board space requirements of today's most highly integrated competitive alternatives, enabling equipment manufacturers to dramatically increase the port density of their 10 Gbps optical transport equipment. In addition, the high degree of programmability embedded in the chip will enable a new level of network operations and maintenance flexibility unparalleled by today's systems.
The BCM8511 is targeted for use in DWDM transmission equipment and terminals, DWDM regenerators, and DWDM cards on SONET/SDH add/drop multiplexers and cross-connects. Compared to competitive alternative solutions, the BCM8511 reduces the total component count for a DWDM solution from three chips to a single chip. Broadcom's single-chip solution has a power dissipation of only 2.2 Watts. Competitive alternatives dissipate between 6 to 9 Watts, and take up to 4 times more area on the printed circuit board. These power and area savings can directly translate into higher port densities on the line card, thereby enabling higher DWDM channel count while leveraging existing fiber networks.
The device supports the emerging International Telecommunications Union (ITU) G.709 recommendation for the Optical Transport Networking (OTN) digital wrapper standard with embedded Forward Error Correction (FEC). The digital wrapper provides a standard method to encapsulate any traffic payload with FEC. This enables transmission over longer network distances without the need to use expensive signal regeneration.
The BCM8511 integrates six major functional blocks, including a digital wrapper encoder and decoder, a FEC encoder and decoder, a 10 Gbps transceiver and a SONET/SDH framer with performance monitoring logic. Each of these blocks can be independently selected or bypassed to accommodate any DWDM regenerator or terminal application. When not in use, the functional blocks can be powered down to minimize power consumption in the application.
Broadcom's BCM8511 integrates a 10 Gbps multi-rate transceiver supporting serial interfaces of 9.953, 10.664 and 10.709 Gbps. The transceiver exceeds all ITU and Telcordia jitter generation performance requirements. It also provides optional parallel 16-bit interfaces operating at 622, 666 or 669 Mbps for some terminal applications.
The BCM8511 is packaged in a 31 mm x 31 mm plastic BGA and is priced at $495 in 50K quantities. The chip is currently sampling to Broadcom's development partners. Production quantities are currently scheduled for availability in October 2001. Broadcom also offers a complete evaluation and design kit, which includes documentation, development boards and related software.