LSI Logic Unveils Next Generation Chip Packaging System
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LSI Logic Corporation today announced its newest packaging, flxI/O(TM) flip chip, for high-performance products in the communications and storage markets. flxI/O flip chip is LSI Logic's third generation of organic flip chip packaging products, offering ASIC/SOC designers improvements in signal I/O density, electrical performance and a significant reduction in die size, when compared to peripheral I/O packages.
Rather than restricting signal I/Os to the periphery of the die, flxI/O flip chip uses an area array approach for signal I/O placement to optimize die size and increase signal I/O counts. flxI/O allows signal I/O placement anywhere on the die, giving designers the flexibility to realize up to 60 percent die size reduction or increase signal I/O density up to 65 percent. All LSI Logic flip chip packaging families, including flxI/O, are ideally suited for communication applications requiring high speed, highly reliable data interfaces at rates of 5Gbits/second and beyond. This includes LSI Logic's high-speed data transfer technologies, Gigablaze(R) and HyperPHY(R).
LSI Logic's flxI/O uses an organic substrate material similar to that used by the FPBGA-package family. Organic substrate technology offers greater signal density and improved electrical performance than ceramic. The use of an organic substrate enhances solder ball interconnect reliability, as the coefficient of thermal expansion between the package and the printed circuit board are closely matched. This is particularly important as the body size of the package increases beyond 35mm/side.
Standard flxI/O packages are available immediately in high volumes to LSI Logic customers in body sizes from 31mm to 50mm/side, with ball counts from 896 to 2397. Chip designers can also benefit from the automated package tools that LSI Logic has developed for its flxI/O packages within its advanced FlexStream(R) tools suite. The FlexStream system integrates best-in-class LSI Logic tools with third-party EDA tools, creating a complete system-to-silicon design environment.