AMD is proposing a new set of x86 processor extensions. As Internetnews.com reported last week, the SSE5 are targeting markets where AMD sees room for performance improvement.
The SSE5 extensions cover three primary areas: high-performance, compute-intensive applications, such as financial simulation and life sciences; multimedia applications, including high-definition video encoding and image processing; and security applications, such as secure transactions and hard-drive encryption.
The extensions are being made public today; AMD will engage developers and OEM partners over the course of the development. Leendert Van Doorn, AMD senior fellow, told Internetnews.com that the extensions are for the Bulldozer architecture, due in 2009, so there will be plenty of time for developers to make suggestions for changes or improvements.
Analyst Rob Enderle thinks AMD has a better approach when it comes to extending the x86 architecture beyond its basic design. “Intel gets an idea in their head of where things are going and then goes off and does it. AMD tends to listen to developers a lot more. One of the big differentiators this decade is they talk to OEM and developers and design around that,” he said.
While AMD adds the 47 new instructions with SSE5 to its processors, AMD is also looking to be more power efficient and shrink the die. Bulldozer will be 65nm instead of the 90nm design of current chips. “So what we’re doing is being smarter about the instruction set and getting more work out of the instruction set,” said Van Doorn.
SSE5 accelerates traditional compute intensive workloads by improving communication between the cores and reducing the number of instructions needed per cycle. It also introduces the concept of combined instructions, such as fused multiply.
For example, if a pair of operations involve a mathematical step and then performing an action based on the results, that becomes a single operation instead of two. In some cases, this means the same task a chip does now will require fewer operations. A 4-by-4 matrix multiply required 20 instructions under SSE5 versus 34 instructions under SSE4.
For encryption, there will be native instructions that could result in a five-fold improvement in encryption. CODEC
All of this will be done openly, with the full SSE5 specs published on AMD’s site and open for discussion, just as it did with 3Dnow! and the x86-64 specs. “We want to have a dialog with the community on how to expand the x86 instruction set out in the open. That’s why we’re releasing this instruction set now more than two years before shipping a product,” said Van Doorn.
Extensions are how Intel and AMD differentiate, and they usually end up cross-licensing them, so there are no huge compatibility problems, said Enderle. He thinks there could be some real value in SSE5 when it ships, but adds that’s a long way of.
“It looks like they could provide a level of value. It would be nice to hear back from customers that they agree but I haven’t heard that yet.”
