AMD’s Road Leads To Barcelona

AMD  is itching for a fight with Intel, preparing for the next round of the server rumble with the upcoming Barcelona chip.

The No. 2 chipmaker is starting to release details about its next-generation server processor, the follow-up to its highly-successful Opteron chip.

Code-named Barcelona, the new chip is a quad-core design that tweaks the existing x86-64 processor architecture.

AMD expects to ship Barcelona chips by the middle of this year. In a meeting with this week, AMD officials emphasized several key differentiators over the Intel  quad-core server chip, the Xeon 5300, or Clovertown.

First, the Barcelona chip is a native quad-core design, not two dual cores glued together like the Xeon 5300, AMD officials claim.

The memory controller for Barcelona is built into the chip and not external, like the front-side bus design Intel uses, leading AMD to claim greater performance because the chip’s four cores are not getting bottlenecked going through one gateway.

Despite the big gain in performance over the previous generation, Barcelona will have the same power consumption levels, with 95- and 68-watt designs.

So even though the wattage hasn’t gone down, the increase in processing power turns into a 60 percent-per-watt performance gain, according to Randy Allen, vice president of the server and workstation division at AMD.

Allen said there’s an 80 percent scale over dual core processors; AMD’s own benchmarks put it well ahead of the Xeon 5300 in terms of performance.

“We took their best punch with Clovertown and this is our response,” he said.

Second, AMD designed the hardware to be easily upgraded. An existing Opteron server can be upgraded by removing the old processors, placing the new Barcelona chip in the socket, and performing a BIOS  upgrade.

AMD also took pains to support virtualization by working with VMWare, Xen and Microsoft to create AMD-V the company’s hardware-assisted virtualization technology.

Barcelona also tweaks the existing design of the x86-64 processor, but those tweaks are significant.

Streaming SIMD Extensions (SSE) have been expanded from 64-bits to 128-bits; the data cache bandwidth has been doubled to 2x 128 bit loads per cycle; and the L2 cache bandwidth has also doubled, to 128 bits per cycle.

Also, the memory controllers now support full 48-bit addressing, which could allow for up to 256 terabytes  of physical memory. Yes, 256TB of memory.

The AMD architecture has also been designed from to operate in a multi-processor, multi-core environment, so its scalability is not the issue facing the company, said Dean McCarron, president of Mercury Research.

AMD’s problem is building it. Intel has a distinct advantage in manufacturing. It can make more chips, make them faster and make them smaller. AMD won’t be using a 45-nanometer die size until the end of the year, while Intel is already on 45nm.

So it becomes a competition of trade-offs.

“AMD will have the architecture that tips the balance of scalability in their favor, but Intel has the manufacturing and pricing advantage,” McCarron said.

But he added, AMD is in a significantly better position now than it was in 2003, when Opteron was introduced and it had no server share and no OEMs. Since then, it has signed up Dell , IBM, HP , and Sun.

“The inroads they’ve made in servers have been impressive. They went from zero to a respectable share. That’s the reason we are in the environment we are in today, which is both companies being competitive,” said McCarron.

AMD stock dropped four percent today after it reported earnings for the fourth quarter of 2006.

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