gave a preview into upcoming processor plans, laying out what’s ahead with its forthcoming chips, codenamed “Penryn” and “Nehalem.”
The company’s strategy is to introduce a new microarchitecture every two years, with a bump in performance in between. The Core technology released last year gets a bump in Penryn and Nehalem, due in 2008, will be the new architecture.
As such, Nehalem will feature some major advances. The processors will have up to eight cores and Intel plans to bring back a blast from the past, the Hyperthreading technology first introduced in its early Pentium 4 processors. Each core in a Nehalem processor will be able to process two threads, meaning an eight-core processor can handle up to 16 threads.
The other notable change in Nehalem is that Intel will finally move away from the front-side bus architecture and put an integrated memory controller directly on the CPU, along with interconnects, which are high bandwidth serial point-to-point buses to feed the Nehalem core.
The design change is a shift for Intel, which has defended its front-side bus architecture in the past year, especially as rival AMD continued to build market share with processors built on direct-connect architecture.
But Intel has long argued that its architecture was also about power savings, a key feature with the next processor family. Tony Massimini, chief of technology for Semico Research, agreed. He maintained Intel could have done integrated memory years ago but it would not be economically feasible.
“Their business is built on doing volume, not high-end niches,” Massimini told internetnews.com. “It comes down to how many transistors can we get into in a given die area. Now that they have 45nm fabrication, they have more room to work with.”
He added that while AMD has had an integrated memory controller for years, Intel’s benchmarks have been competitive or even better than AMD’s in many areas, so why rush the expense of moving off of FSB?
Penryn chips will operate at the same or less power than Intel’s current dual core processors and introduce a new advanced power management state called Deep Power Down Technology. Intel claims that this new technology reduces the power of the processor during idle periods to such an extent that internal transistor power leakage is no longer a factor.
Despite Penryn being the refresh and not the performance leap of a new architecture, it’s getting quite a boost. The clock speed will be around 3.3GHz, up from the 2.93GHz of current top of the line Core 2 processors, and the bus speed will be 1333MHz or even 1600MHz. The current bus runs at 1066MHz.
The Penryn family, due later this year, will be the first to feature 45nm design and the high-k and metal gate technology announced earlier this year. There will be a total of six processors in the Penryn family, dual and quad core, all sold under the Core brand name for desktops and mobile.
Penryn will also see the debut of Streaming SIMD Extensions 4 (SSE4) instructions and enhanced virtualization support. Penryn chips will speed up virtual machine transition (entry/exit) times by an average of 25 to 75 percent. It will also have a 50 percent larger L2 cache, up to 6MB for dual core and 12MB for quad core in some versions.
Nehalem will introduce dynamically scalable and managed cores, threads, cache, interfaces and power, the new SSE4 instruction set along with new ATA instructions, new multi-level shared caches and a high performance integrated graphics engine for certain chips.
This year, Intel is changing how it runs its Intel Developer’s Forum conference. Normally, the chip giant has held two shows in San Francisco, Spring IDF and Fall IDF, plus smaller scale shows around the world. But this year, it’s hitting the road.
“We decided to have one worldwide IDF in a very happening, central location and China is a happening place right now,” George Alfs, a spokesman for Intel, told internetnews.com. There will still be a fall show in the U.S., but it seems likely next year the big show will again be in an international location.
This article was updated to include analyst’s comments related to Intel’s use of the Front Side Bus in its processors.