Intel has built a new chip with 500
million transistors using the latest advancements in nanotechnology, the
company said Monday.
The Santa Clara, Calif.-based company said its
fully functional, 70-megabit static random access memory (SRAM)
were built using 65-nanometer (nm) process technology, are scheduled for
production starting in 2005. The company’s vision is to take its 65nm
technology and include it in its dual-core processor designs with more than
a billion transistors on a chip.
The company said increasing the number of transistors and shrinking the
size of the processors will also let it add other features usually
reserved for the surrounding chipsets or software applications, such as
virtualization and security capabilities.
In November 2003, Intel announced it used its 65nm process to build
4-megabit SRAMs. Since that time, the company has built fully functional
70-megabit SRAMs on this process with a very small die area of 110
millimeters. Small SRAM cells allow for the integration of larger caches in
processors, which increases performance. Each SRAM memory cell has six
transistors packed into a very small space. For example, some 10 million of these
transistors could fit in one square millimeter, roughly the size of the tip
of a ballpoint pen.
Intel’s 65nm transistor designs seen by internetnews.com have a
reduced gate length of 35nm and a gate oxide thickness of 1.2nm. Intel said
the reduced gate capacitance ultimately lowers a chip’s active power. The
new process also integrates eight copper interconnect layers and uses a
“low-k” dielectric material that increases the signal speed inside the chip
and reduces chip power consumption.
Intel has also implemented “sleep transistors” in its 65nm SRAM. Sleep
transistors shut off the current flow to large blocks of the SRAM when they
are not being utilized, which eliminates a significant source of power
consumption on a chip. This feature is especially beneficial for
battery-powered devices like laptops.
“Intel has been actively working on the power and heat dissipation
challenges faced by the semiconductor industry,” Sunlin Chou, senior vice
president and general manager of Intel’s Technology and Manufacturing Group
said in a statement. “We have taken a holistic approach by developing
solutions that involve systems, chips and technologies, and include
innovations on our 65nm technology that go beyond simply extending prior
techniques.”
Intel’s future is certainly the sub-90 nanometer space, which is becoming
one of the fastest emerging areas in the sector. Currently, the company is
shipping its Pentium 4 “Prescott” processor based on the 90nm process and is
introducing its second generation of Intel-strained silicon in its 65nm
chips. The technology increases transistor performance by 10 to 15 percent
without increasing leakage.
Mark Bohr, Intel senior fellow and director of process architecture and
integration, told a group of reporters that the company has now reached the
crossover point where it is shipping more chips produced on the 90nm process
than on the 130nm process.
“Many companies are pursuing this technology and claim that they have
strained silicon, but no one has that PMOS strain and no one has matched or
implemented what we have done with PMOS,” Bohr said during a phone briefing.
“It’s safe to say that our competitors have a modified
version of one portion of strained silicon but they do not have it in either
production or in development.”
Beyond 90nm, Intel has set a tentative roadmap to release 65nm processors
by 2005, 45nm ones by 2007 and 32nm chips sometime in 2009. The company is
not alone when it comes to sub-90nm aspirations. IBM and
Texas Instruments have also announced their plans for 65nm
processors.
Intel said it will discuss its 65nm logic technology in detail as part of
a white paper it will present at the IEEE International Electron Devices
Meeting in San Francisco in December.
