SAN FRANCISCO –- Just a few years ago, the Intel Developer Forum seemed to be about everything but CPUs. Not this time. CPUs were the first, last and everything else that CEO Paul Otellini discussed here today.
Having shed its distractions, a few thousand employees and some market share in the process, Intel is focused on CPUs more than it has been in years.
With the Core 2 Duo on the market, Intel
is now looking at releasing four core chips by year’s end.
Core 2 Extreme Quad Desktop, code-named Kentsfield, will be up to 70 percent faster than the current top-end desktop chip, the Core 2 Extreme X6800.
Xeon 5300, code-named Cloverfield, will replace the extremely popular 5100 line that’s only been on the market for three months.
Otellini said that more than 1 million Xeon 5100 processors have been sold in its first three months of release, impressive for a server.
“Much has been written in the past year about Intel losing its leadership in the marketplace,” Otellini said during the morning keynote. “I believe we have regained our leadership and these are going to gain share in the marketplace.”
Intel plans to roll out new microarchitectures every two years, starting with Core 2 this year, Nehalem in 2008 and Gesher in 2010. Intel is charging forward with three massive new fabrication plants and plans to reach 45nm die by next year.
“We’re not slowing down on Moore’s Law. We have the technical capacity to make it happen,” said Otellini.
Core 2 Quad chips won’t be in notebooks any time soon due to their heat envelopes for quad core chips.
Instead, next year will see the release of Santa Rosa, a new Centrino chip with the Core 2 Duo architecture, integrated graphics that support Vista’s Aero interface, 802.11n networking, NAND Flash memory and new manageability and security features for the enterprise.
This will be the first time NAND memory, Flash memory used in place of a hard disk, is used in a notebook. Data that’s frequently accessed is stored in this flash memory instead of a hard disk.
By using Flash memory as a large cache, it cuts down on hard drive access, boot time, and wake from hibernation. Otellini predicted faster boot times, twice the application performance and cutting battery power consumption in half.
Reduction of CPU power isn’t just a concern for datacenters, it’s also on the minds of mobile devices, too. Intel is promising to cut battery consumption in half next year, and reduce power consumption ten-fold by 2008.
CTO Justin Rattner followed Otellini to discuss power-related issues and the future datacenter, or what he called the megacenter.
He predicted that 25 percent of servers would be going into datacenters with 100,000 servers or more in the next five years.
The growth in server farms can’t be underestimated. To provision a million servers today, Rattner pointed out you need 800,000 square feet to house the equipment. That’s the size of 18 football fields.
The farm would require 500 megawatts to power it, which is enough for 278,000 homes.
“It’s hard to imagine we won’t be impacted by this in a fundamental way,” he said.
But while Intel works on reducing the power consumption of its Xeon chips, it also looked at other parts of the power chain.
The typical datacenter delivers only a third of the measured power to the computers.
The other two-thirds of power literally goes up in smoke as wasted heat due to inefficient conversions between alternating current (AC) and direct current (DC).
Through its own power supply research, Intel was able to create a 90 percent efficient power supply that will provide a 60 percent increase in servers per megawatt in the datacenter.
That translates to 600 more servers for the same power, or just save the energy.
Finally, Intel gave some clues to where it’s going in the future.
In addition to demonstrating its new laser-based processor, the company offered the first details of its Tera-scale Computing Research Program.
The project, in conjunction with the University of California at Santa Barbara, is the world’s first programmable processor said to deliver 1 trillion floating point operations, or teraflops, per second.
The chip had 80 programmable floating point processors each, with on-chip memory, capable of a teraflop of bandwidth throughput.
This will allow for high-speed computing like video searches and real-time gaming, said Rattner. However, the chip is at least five years from availability.