CORRECTED: Intel today showed off its latest science project, a teraflop processor with 80 cores that, while it will never be productized, will help the company in its future CPU projects.
The CPU was intended to be a research project into how to develop an effective and efficient multicore processor, since Intel sees cores, not clock speed, as the means for performance advancement in the future.
“To increase performance, we need to scale out to parallelism. But then you have new issues to deal with, such as all the threads, an operating system that can parallelize the threads, caches that can handle simultaneous processes,” said Sean Koehl, technical strategist of the Terascale program at Intel .
The experiment proved insightful for Intel. “We have learned we’re able to create a high speed mesh that can handle terabits of data per second,” Koehl told internetnews.com. “Something you need to scale these processors is high bandwidth for core-to-core communication.”
The chip is not based on x86 or any existing design. The 80 cores are all floating point engines, each with its own high-speed controller for communicating with the other cores. The chip uses Intel’s new 45nm design and the new metals design recently announced that will allow for even smaller processor design in the future.
This means energy efficiencies, such as the cores turning each other on and off to save power. “We think this is how we will scale performance in the future. The old manner of turning up clock speed is not proving energy efficient,” said Koehl.
One of the ongoing efforts is learning how applications operate in parallel. The terascale chip literally breaks an application or task into 80 pieces and each core does its own small part in the computation process before the entire process is reassembled.
However, learning how to effectively design applications to run in parallel is a long process. Because they all behave differently, some applications can achieve the teraflop of throughput this chip is said to offer, while others run considerably slower.
It’s always hard to say how research will pan out in product directions, said chip analyst Nathan Brookwood of Insight64. “However, it’s pretty clear that the future is multicore, possibly massively multicore, and the programming challenges to taking advantage of dozens of cores are substantial. So to the extent Intel and its researchers extract some learning from this, all of that is potentially very helpful,” he said.
Putting a teraflop of power on one chip is certainly extraordinary, but conceptually, Brookwood said the teraflop chip isn’t a whole lot different from IBM’s BlueGene and the ASCI Red project from Sandia National Labs. Both rely on hundreds of processors linked by a high-speed network.
Corrects spelling of Sean Koehl’s name.
