New batches of products hitting store shelves today promise some of
the fastest chip-to-chip interconnect technology around.
The new products conform to HyperTransport Specification 2.0, which
supports up to 22.4 gigabytes/second aggregate bandwidth and includes
64-bit processors, I/O chipsets, silicon IP and development tools.
Companies like AMD, Agilent, Dolphin, FuturePlus, GDA, SiS, ULi and VIA
are introducing the first wave of products.
The addition of technology based on the new specification should
help support predictions by the HyperTransport Technology
Consortium and analysts at IDC that HyperTransport port shipments
will grow from more than 30 million ports in 2003 to more than 200 million ports
in 2006.
Already, the original HyperTransport specification powers such
devices as Microsoft’s Xbox, Apple’s Power Mac G5, Cisco’s high-end
routers, IBM’s and Sun Microsystems’s servers, notebooks, Tablet PCs
based on Transmeta’s Efficeon-processor, and AMD’s Athlon64- and
Opteron-based PCs, servers and supercomputers.
“The industry’s rapid adoption of our latest specification is a
strong endorsement of the technical advancements embodied in
HyperTransport technology,” Mario Cavalli, general manager of the
HyperTransport Technology Consortium, said in a statement. “It also greatly adds to the comprehensive set
of HyperTransport-based building blocks that the industry is leveraging
in high-performance designs.”
The technology is sharply contrasted with Intel’s
traditional “Northbridge/Southbridge” designs, which Mark Stahlman, former AmTech
research analyst, characterized as “aging.”
“Memory standards are very long-term evolutions (e.g. three to five years).
And the benefits in memory latency and increased bandwidth from adding
multiple processors with integrated controllers would seem to far outweigh
the added design complexity issues,” Stahlman wrote in a December briefing to investors.
HyperTransport is actually the new name for Lightning Data
Transport, which was jointly developed by AMD. The
technology can be used to improve performance in PCs, servers and
embedded systems.
Release 2.0 introduces three more powerful bus
speeds and mapping to PCI Express
speed capability ranges from the 1.6 Giga Transfers/second (GT/s) of
Release 1.1 Specification to 2.0, 2.4, and 2.8 GT/s using dual-data rate
clocks at 1.0, 1.2, and 1.4 GHz. The electrical protocols
supporting the new clock rates are also backward compatible, the
consortium said.
