UPDATED: SAN FRANCISCO — AMD today offered industry observers a look at a very different roadmap for the next two years of its server processors, changing its plans from just a few months ago to focus on offerings that will scale to up to 12 cores without increasing power demands.
In the process, AMD (NYSE: AMD) also will embrace an idea it has ridiculed for years: the multi-chip module (MCM).
One thing that remains the same is the next iteration of quad-core Opterons, codenamed “Shanghai.” Due later this year, these will be 45nm, a die shrink from the 65nm process used in the current crop, Barcelona. Shanghai also will be designed to fit in existing servers with the same Socket F design used by Opteron processors today.
The processors will have 6MB of L3 cache, three times Barcelona’s cache, and will support 800MHz DDR2 memory. The chips will also come with AMD-V, a virtualization technology for better processor clock scheduling. Clock speeds were not disclosed.
One element of the roadmap that may surprise observers is that AMD has no plans to move to high-k metal gate technology, which it can get from its chip partner IBM (NYSE: IBM).
Even though high-k metal gate has shown clear benefits for Intel’s (NASDAQ: INTC) new Penryn processors, Randy Allen, general manager of AMD’s server and workstation division, said the company would stick with the immersion lithography it uses for 45nm designs.
After “Shanghai,” the roadmap changes. As of December, AMD’s next-generation platform was going to be the eight-core “Montreal” design, which had been slated for 2009.
AMD decided to alter the roadmap after determining that there was more performance headroom in its current platform and architecture, and after customer feedback encouraged them to push the bar higher with the existing platform. As a result, Barcelona/Shanghai will go to six cores rather than a wholly new eight-core design.
The road to Istanbul
For the second half of 2009, AMD now plans to scale down Montreal into the six-core design codenamed “Istanbul”. Istanbul will be a native six-core design, will be Socket F-compatible and includes a 6MB L3 cache, HyperThreading 3.0 and AMD-V virtualization support.
Unlike Intel’s planned six-core processor, Dunnington, Allen said Istanbul is meant for mainstream systems based on two or more sockets, which make up the bulk of server sales. Dunnington, meanwhile, is only for the multiprocessor server market, in which systems use four or more chips — something of an industry niche.
AMD’s new roadmap also keeps the low-end in mind, with upcoming single-socket processors based on the Barcelona design. Budapest will be a quad-core processor designed for single-socket servers, and is due in the second half of this year. It has 2MB of L3 cache, DDR2 memory support and HyperThreading 3, just like Barcelona.
In the second quarter of 2009, Budapest will be succeeded by Suzuka, a single processor version of the Istanbul chip, with four cores, 6MB of L3 cache, DDR3 support and a 45nm design.
In 2010, AMD will release more high-end processors — Sao Paulo and Magny-Cours, both of which will feature new core technologies and use a new socket/platform, Maranello, previously codenamed “Piranha”.
Sao Paulo is a six-core chip with 6MB of L3 cache while Magny-Cours is a 12-core chip with 12MB of L3 cache.
In addition to featuring the new Maranello socket design, both will support a new generation of HyperThreading, as well as support for higher-end DDR3 memory and advanced clock switching to shut down idle cores.
What’s good for the goose…
Magny-Cours, meanwhile, will achieve a 12-core design by putting two Sao Paulo chips on one die in the same sort of multi-chip module design Intel used in its quad-core Xeon — a design choice that AMD had previously ridiculed.
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However, this change in design strategy makes a lot of sense to Dean McCarron, president of Mercury Research, which follows the semiconductor market.
“What I am seeing overall is they are making business decisions when they are making their technical decisions,” McCarron told InternetNews.com.
“AMD is a little more sensitive to taking big risks without making financial reward now,” he said. “When you have to get financial results, you get conservative.”
Consequently, rather than doubling a quad-core design as it would have with Montreal, AMD instead opts for a six-core design, which will be less ambitious but will mean higher yields. That translates into lower cost of manufacturing.
Then, rather than go through the agony of making a native 12-core chip, it takes a page from the Intel playbook and uses an MCM design for Magny-Cours.
“So it makes a lot of sense from a manufacturing perspective to make both steps,” McCarron said. “It’s a big roadmap change, but there’s a benefit coming from it.”
One big difference between Magny-Cours and Sao Paulo will be clock speeds. Because AMD has pledged both will fit in the same power envelope, it means Magny-Cours’ 12 cores will have to run slower than the six in Sao Paulo.
“Given the industry has made it very clear it wants to hold down on the power envelope, we can deliver higher clock speeds with fewer cores,” Allen said. “At 12 cores, you have to run slower to keep the processor in the same power envelope.”
McCarron said this could help AMD stay competitive with Intel.
“You have a number of avenues where they have to be competitive, like price and risk versus reward. They’ve lowered the risk and see a higher reward with this version of the roadmap as opposed to doing a monolithic eight-core design.”
The change in plans — and AMD’s newfound risk aversion — come as the company is seeking to rebound after a painful, protracted delay in shipping Barcelona.
One of the reasons the company lagged in getting Barcelona out the door had been the TLB errata bug, though Allen today said the bug had been extremely rare and very hard to trigger.
Still, he said AMD decided it was still worth the bad publicity to hold off shipping the processors until it was fixed.
“We ran the risk of data corruption and we couldn’t risk something like that,” he said. “If it were just something that caused a system crash, we might have been able to push through that.”
Still, there is one computer doing just fine with those flawed Opteron chips: Ranger, the Sun Microsystems supercomputer at the University of Texas at Austin. With 16,000 processors — for a total of 64,000 cores — Ranger has more computing power than all other open scientific clusters combined, Allen said.
Sure, there are faster supercomputers — like Blue Gene/L and Red Storm — but they are operated by the military and not for public use. Any researcher can rent time on Ranger to do things like climate modeling or astronomical calculations, and Allen said time on the system is constantly sold out.
Update adds new information on the architecture of Magny-Cours and comments from McCarron.
