Intel Clarifies The Road Ahead

SAN FRANCISCO, Calif. – Intel on Monday gave further details on some of its forthcoming processors in advance of the spring Intel Developer Forum (IDF) conference, to be held in Shanghai, China, in early April.

First up, the company discussed Dunnington, the six-core processor that will be the last major processor release before Intel’s newer architecture, Nehalem, is released. Dunnington is for multiprocessor servers, meaning four or more processors, and will be socket compatible with Caneland, the MP server processor it released last year.

“Dunnington is designed to enhance the Caneland platform while being constrained by an exact match into that platform,” said Steve Smith, vice president and director of the digital enterprise group at Intel (NASDAQ: INTC). “The most likely scenario for it is where an IT manager qualifies the platform and knows their upgrade path into the future and that they get a boost when we ship the chip.”

Intel’s biggest effort is Nehalem, the new product line that marks the end of the frontside bus and external memory controller, as it will have an on-chip memory controller, just like AMD’s Opteron and Athlon processors.

Nehalem is set to ship to OEMs in the fourth quarter of this year. The architecture will be the successor to Intel’s successful “Core” introduced in 2006. The Nehalem family of processors will have anywhere from two to eight cores and add Simultaneous Multithreading (SMT), a return of the old HyperThreading first introduced in the Pentium 4 back in 2000.

Smith explained that multithreading wasn’t so much dumped as it just fell to the back of the line. “There was only so much change they could tackle in the Core architecture and we simply couldn’t get it into the schedule. We had to prioritize benefits of each design decision,” he explained.

Nehalem’s QuickPath interconnects will provide extremely high-speed connections between memory and the CPU at up to 25.6GB per second. Each core will have its own 32k L1 cache, 256k L2 cache and be spanned by 8MB of L3 cache.

This will help improve performance by sharing data between processor cores without having to exit the CPU and go through the frontside bus, as it does now. In addition, Nehalem will use what Intel called an inclusive cache policy, so when one core goes out to memory to get data, it already knows the other three cores and caches don’t have that particular piece of data and the cores/caches are not interrupted.

Nehalem will support three memory channels per socket, and each channel can support three DIMMs, so each socket will support nine DIMMs total. Nehalem will support DDR3 memory or newer RDIMM and UDUMM memory, but not the more power-hungry FBDIMM. This will give Nehalem Xeon processors four times the performance of the Harpertown line.

Intel also discussed the Larrabee Architecture for visual computing. Larrabee is a many-core design using micro-cores, smaller, pared down cores built on Intel’s architecture and instruction set. It will come with a significantly different coherent cache design to support the many-core architecture.

It will be used specifically as a co-processor for graphics and video rendering, processing and imaging, so it will be used in systems along side a CPU and GPU. Intel has no set release date planned but expects to demonstrate it later this year.

Finally, Intel discussed Intel AVX, or Advanced Vector Extensions for compilers that will increase performance in floating point, media, and processor-intensive software. Support for it will not appear until the “Sandy Bridge” family of processors is released in 2010.

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