Intel’s Future Is Integrated

Intel and SoC


Research papers released at the International Solid-State Circuits Conference (ISSCC) are rarely light reading, unless you have a doctorate in electrical engineering. That’s because they are long-range visions of where semiconductor development is headed in the next five to ten years.

For Intel, that vision is focusing on system-on-a-chip (SoC) design — in which all of a computer’s chips are whittled down and integrated onto a single piece of silicon. According to papers Intel plans to present at ISSCC next week in San Francisco, the technology could encompass everything from high-end server products down to embedded processors, such as wireless networking chips.

The world’s largest chipmaker is already heading in that direction: Its Core i7 processor (codenamed “Nehalem”) integrates the memory controller onto the CPU, and Intel (NASDAQ: INTC) is working on a later Core i7 product that will integrate a GPU onto the die.

Intel will give a deeper look at SoC’s more immediate future when it presents a paper on its new high-end processor, Nehalem-EX. The chip, first discussed at the Intel Developer Forum last year, is a 2.3 billion-transistor monster and the largest processor Intel has ever made. It contains eight cores and the ability to run two threads per core.

Intel’s interest in SoC technology comes as it and other chipmakers explore ways to tame the number of chips filling everything from your smartphone to your server, and in doing so, increase performance. Instead of requiring chip-to-chip communication — which increases latency — SoC allows for far quicker communication between transistors on the same piece of silicon.

However, it’s not clear how much of the SoC projects discussed at ISSCC will be making their way into live products. Intel’s efforts in the area remain lab work for the moment, and aside from the Nehalem-EX, the company has not disclosed specific plans for releasing these technologies or incorporating them into a product.

Yet SoC remains a compelling prospect, and one that’s only now becoming practical, according to Soumyanath Krishnamurthy, an Intel Fellow and author of a paper to be presented at ISSCC.

“Technology has to be at the point where we could do it,” Krishnamurthy told InternetNews.com. “It has to be cost-effective at the right time. Scaling lets us do more and more every generation.”

SoC’s capabilities will be the subject of another of the 15 papers Intel researchers will present at the conference.

In “The New Era of Scaling in an SoC World,” Intel maps out how newer technologies are making it possible to continue increasing the number of transistors crammed onto a chip — keeping Moore’s Law going into the realm of SoC. The result, according to the researchers, could be a new category of highly integrated, purpose-built designs and products.

Wireless aspirations

CPUs aren’t the only chips Intel hopes to see crammed into tinier spaces. The company’s engineers are looking at integrating more wireless technologies onto a single die. Until recently, Wi-Fi and WiMAX or 3G and Bluetooth couldn’t even co-exist on the same piece of hardware. They’re available now, but only as two separate chips.

[cob:Special_Report]Three of Intel’s ISSCC papers will cover a move to bring more radio components — parts that transmit a wireless signal — to silicon, a move that could improve cost and performance. The company wants to not only put multiple wireless frequencies on a single chip but make them more digital-friendly, with less interference.

That’s no small order. Today’s wireless transmissions are analog because “that’s the way radios like to work,” Krishnamurthy explained: The signal coming off the air is analog, but in the chip, it’s purely digital. That makes it a challenge to integrate three or four protocols that all have different analog-to-digital conversions.

Page 2: Cutting wireless interference and bringing SoC to graphics

Intel and SoC

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At the same time it’s tackling that problem, Intel wants to reduce interference by making designs quieter and cleaner — so you don’t get that annoying buzz from placing your mobile phone too close to computer speakers or a landline.

Intel is also working on bringing gigabit LAN technology to wireless. That requires a very fast analog-to-digital converter.

It also involves dealing with serious power consumption issues. As you go up in transmission speed, power consumption goes up almost on a one-to-one ration, if not worse, Krishnamurthy said. The leap from 802.11g wireless connectivity — at 54 megabits per second (Mbps) — to 300 Mbps with 802.11n doubled the amount of power consumed, which he said was the reason that it took so long to make the transition.

Continuing the trend by going to gigabit wireless would be hell on laptop batteries. As a result, Intel is looking at how to increase throughput while avoiding a concurrent rise in power consumption.

Intel also is turning its attention to the graphics front, particularly for mobile devices. As graphics processors are shrunk to fit into smaller devices, more has to be done with fewer transistors. At the same time, Intel is hoping to get power consumption down.

Part of the way it aims to achieve this is through a SIMD (short for “Single Instruction, Multiple Data”) architecture, which is used to achieve parallel processing in graphics processing .



Intel researchers plan to describe the technology in another paper to be presented at ISSCC. The show runs Sunday through Thursday in San Francisco.

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