Monday took the wraps off of a new series of 90-nannometer chips designed for the communication and networking sector.
Based on its Instant Silicon Solution Platform (ISSP), the next generation ISSP2 series of structured ASICs
The Tokyo-based electronics manufacturer says its microcontrollers are faster and more inexpensive than the most advanced FPGAs on the market.
“With the new ISSP2 devices, we are able to further distance ourselves from high-end FPGAs in terms of performance and integration. Our customers can customize designs very quickly at a very small volume and very competitive cost,” NEC Electronics general manager Dr. Hitoshi Yoshizawa said in a statement.
The company said its ISSP2 device architecture is a five to seven metal-layer design with two easily customizable layers to meet individual design requirements. The bottom layers are predefined with NEC Electronics’ IP and DFT blocks, and include circuitry to minimize signal integrity, power routing and clock skew issues.
NEC introduced its ISSP1family back in March 2002 with its ISSP1-HSI (high-speed interface) family debuting a year later. The company says its architecture addresses design and manufacturing cycle time challenges of mid-volume custom ASICs. The idea is to tackle the concerns by embedding “design for test” and “clock tree synthesis” circuitry along with power lines, “analog phase-locked loops”, SRAM
The new ISSP2 devices incorporate a 10 Gbps single-port SerDes interface, as well as a next-generation 3-Gbps Serial ATA interface, which it says makes the devices ideal for high-end computing and high-bandwidth networking applications.
Reference design kits, which include device libraries for the new ISSP2 series, are expected to be available by January 2004. NEC says the engineering samples and mass production are on schedule for deliver sometime between April and June 2004.
In addition, NEC Electronics today unveiled its ISSP Open Alliance Program. Under the program, NEC Electronics will establish ISSP-Certified Design Houses, ISSP-Certified Third-Party IP Cores and EDA Vendor Alliances.
For example, GDA Technologies, a design services company focused on designing systems, boards, SoCs, FPGAs and IP from concept to product, will use NEC Electronics’ standard ISSP design flow and libraries. CoreSim, Inc., a product lifecycle management company that uses advanced design analysis techniques to deliver fully backward-compatible FPGA, ASIC and multichip silicon conversions will do likewise. These and other certified design houses will receive training and on-call support as needed, as well as continuous updates for ISSP libraries and design manuals. The design houses will also have access to NEC Electronics’ proprietary design tools as necessary, and be able to add IP from their own portfolios or from external sources. An ISSP-Certified Design House will forward a signed-off netlist or GDSII to NEC Electronics for prototyping.
NEC is also inviting additional third-party IP vendors to port their IP cores to the ISSP platform. After certification by the company, IP cores such as processors and interfaces will be added to NEC Electronics’ IP portfolio. NEC said its Electronics division will then offer an ISSP shuttle service to get vendors on the fast track to validate their IP cores in silicon.