Researchers at IBM Tuesday took the wraps off a new chip design for wireless devices that performs four times better than current transistors and takes up one-fifth the power.
The Armonk, N.Y.-based firm said the new chip is the world’s first bipolar transistor with silicon-germanium (SiGe) base built on complementary metal oxide semiconductor (CMOS)-compatible silicon on insulator (SOI) wafer.
The company said the finished transistors could debut in consumer devices within five years, enabling applications such as video streaming on cell phones. The new designs were first highlighted at an International Electron Devices Meeting (IEDM) in San Francisco back in December. The project is a collaboration between researchers and developers at the IBM Semiconductor Research and Development Center, IBM Research and IBM Microelectronics Division.
“As the wireless industry continues to grow, new devices will require greater functionalities, performance, and reliability from their components,” Dr. T. C. Chen, VP Science and Technology, IBM Research said in a statement. “IBM continues to find new methods to improve chips to ensure that the industry can meet consumer demands.”
Transistors have been shrinking in size for the past 30 years to keep up with the demand for smaller and more intelligent electronic devices. Scaling the transistors or reducing the gate length (the size of the switch that turns transistors on and off), improves the performance and speed of chips as well as lowers manufacturing costs and power consumption.
Compatible with current CMOS
CMOS computing chips show higher performance when built atop a thin SOI wafer. However, traditional SiGe bipolar transistors cannot be built on a thin SOI wafer. Until now, no one had been able to find a technique to combine CMOS and SiGe bipolar onto one wafer that would maximize the performance of both.
The new design lets electrons come down from the poly-silicon emitter, accelerate through the silicon germanium (SiGe) base, and make a turn in the SOI layer towards the collector contact electrode. With zero or low voltage applied to the SOI wafer, the current path in the SOI is long, which results in low electric field in the SOI and makes the device suitable for high voltage applications; with high positive voltage applied to the SOI wafer, the collector contact is virtually extended all the way to the back of the SOI layer under the emitter. The current path is thus shorter, making the device suitable for high-speed applications.
The SiGe BiCMOS transistors are expected to be produced using 65 and 45 nanometer (nm) processes using halo implants and 248nm-wavelength lithography.
IBM researchers were in Toulouse, France this week to present the details of the new chip design at the 2003 Bipolar/BiCMOS Circuits and Technology Meeting.
