Intel has unveiled new memory
technology it says will double the number of transistors it can build on a single processor.
At its development fabrication plant in Hillsborough, Oregon (also known as D1D), the chip making giant said it has built fully functional SRAM (Static Random Access Memory) chips using 65-nanometer (nm) technology, a next generation
high-volume semiconductor manufacturing process. The technology is expected to debut on Intel 300 mm wafers sometime in 2005.
SRAM is a type of memory that is faster and more reliable than the more common DRAM (dynamic RAM). The term static is derived from the fact that it doesn’t need to be refreshed like dynamic RAM. However, while DRAM
supports access times of about 60 nanoseconds, SRAM can give access times as
low as 10 nanoseconds. In addition, its cycle time is much shorter than that
of DRAM because it does not need to pause between accesses. Unfortunately,
it is also much more expensive to produce than DRAM. Due to its high cost,
SRAM is often used only as a memory cache.
The Santa Clara,
Calif.-based company did not say exactly which of its processors would take
advantage of the new memory. But the company’s roadmaps indicate Intel will debut nanometer
Itanium chips about the same time.
Intel’s vision is to take its 65-nm (a nanometer is one-billionth of a meter) technology to one day put a billion transistors on a chip. Intel said the latest process uses a
second-generation version of Intel’s strained silicon, high-speed copper interconnects and a low-k dielectric material. The technique puts eight copper interconnect layers close together and uses a “low-k” dielectric material
“This accomplishment puts Intel’s 65-nm technology on a fast track to
extend our 15 year record of ramping production on a new process generation
every two years. In fact, only 20 months have elapsed since we disclosed
achievement of fully functional SRAMs on our 90-nm process, which is now
ramping,” said Intel senior vice president Dr. Sunlin Chou.
Intel has used its 65-nm process before to make fully functional,
four-megabit SRAM chips with a very small 0.57um2 cell size. Small SRAM
cells allow for the mixture of larger caches in processors, which improve
performance. The company said its SRAM cells have tough operating
characteristics, with a solid noise margin indicating very efficient on/off
switching properties. Each SRAM memory cell has six transistors: 10 million
of these transistors would fit in one square millimeter, roughly the size of
the tip of a ballpoint pen.
When put into mass production, the new 65-nm process chips will feature
transistors measuring only 35-nm in gate length, which by all accounts will
be the smallest and highest performing CMOS
around. By comparison, the most advanced transistors in production today,
found in Intel’s Pentium 4 product lineup, measure 50-nm.
On the manufacturing side of the house, Intel said its own mask making
team has been working to build better processes that extend its existing
193-nm wavelength lithography equipment for use with the 65nm process
generation. The company said it expects to reuse the same 193-nm and 248-nm
lithography machinery that it currently uses on its 90-nm process, as well
as adding some upgraded 193-nm tools. The same techniques will be replicated
in other Intel fabs, the company said.
