AMD Thursday outlined improvements to its transistor technology, which it says should hit volume production as early as 2007.
A primary working parts of a microchip, transistors are microscopic switches that turn the flow of electrical current on and off. The better the transistor performance, the better microprocessor performance or so the popular thinking goes.
The Sunnyvale, Calif.-based semiconductor maker said with the help of IBM , AMD’s new triple-gate transistors use next-generation silicon-on-insulator (SOI) and advanced metal gate technologies. From a side-view, the transistor is looks like a raised, flat plateau with vertical sides.
With flat transistors, electronic signals travel as if on a flat, one-way road. This approach has been the standard in the semiconductor industry since the 1960s. But, as transistors shrink to less than 30 nanometers
AMD said its ultra-thin electrical path uses fully depleted silicon-on-insulator (FDSOI) technology is surrounded on three sides with nickel-silicide metal gates. This combination of FDSOI and nickel-silicide metal gates has the effect of straining the silicon lattice within the electrical path to enhance carrier mobility.
Furthermore, the multi-gate, FDSOI structure increases the effective width of the electrical path in the transistor and also provides better electrical control of this path. These factors combine to provide higher ON current, lower OFF current and faster switching, thereby dramatically increasing the overall transistor performance.
The design lets electronic signals move along the top of the transistor and along both sidewalls. The effect triples the area available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more space.
“This new triple-gate design takes us one step closer to making multi-gate transistors a production reality. It is this kind of research that enables us to deliver higher performance solutions to our customers on an aggressive schedule,” said Craig Sander, vice president of process technology development for AMD. “This multi-gate transistor implementation is highly compatible with current manufacturing techniques, which improves our ability to put this technology into high-volume production.”
If some of this sounds familiar, it’s because Intel unveiled its three-dimensional (3-D) “tri-gate” transistor design last year, which it plans on putting into production around 2007.
The Santa Clara, Calif.-based chip making giant it says their version performs better using less power than traditional planar (flat) transistors. The design is also compatible with the future introduction of a high K gate dielectric for even lower leakage.
Still, AMD boasts its design delivers up to 50 percent better performance than any previously published multi-gate research. So much so that the company claims it surpasses the 2009 requirements set by the International Technology Roadmap for Semiconductors (ITRS).
