ARM Hangs Designs on Multicore Chip

Semiconductor design firm ARM took the wraps
off two new blueprints for embedded processors.

ARM debuted its MPCore synthesizable multiprocessor on Monday, based on its ARMv6 architecture and developed in concert with NEC
Electronics. The design
can be configured to contain one to four processors for electronic
devices like cell phones and video players.

The multiprocessor supports up to four-way cache coherent symmetric
multiprocessing (SMP), up to four-way asymmetric multiprocessing (AMP), or
any combination of both. The first silicon designs are expected to debut in
2005 and support la wide range of operating environments including
ones based on Linux kernel version 2.6. ARM also released an evaluation
system Linux 2.6 OS and development tools to give developers an advanced
look at the blueprint.

ARM said the new designs were necessary to accommodate the increasing
array of multitasking devices, such as a set-top-box that records several TV
channels while sharing home movies across the Internet or an in-car
navigation system that also supports back-seat video gaming.

“Multi-processors are becoming very necessary in the digital home,”
Dave Steer, director of segment marketing at ARM, told
internetnews.com. “Say your device is busy downloading your e-mail,
checking it for virus and filing it away in your inbox, and the user wants to
start to browse the Internet. On a uni-processor these two activities need
to be time-sliced, causing the periods of high background activity to
slow down and make the UI jerky. With multiple processors, both activities
can continue at full speed.”

Steer said the MPCore is flexible because it uses a modified MESI
protocol for improved cache. It also features configurable level 1 caches,
64-bit AMBA AXI interfaces, vector floating-point coprocessors and
programmable interrupt distribution. The processor supports Adaptive
Shutdown of unused processors to reduce power consumption by up to 85
percent, the company said.

Likewise, ARM’s new embedded signal processing core technology,
OptimoDE (DE for Data Engine), is designed to help cut down power drain for
domain-specific applications.

The OptimoDE technology is the first to come out of the acquisition of
Adelante Technologies in July 2003. The framework includes a
configurable Very Long Instruction Word (VLIW)-styled architecture, hardware
configuration tools, C compiler, reference examples and an interface kit.

ARM DSP Program Manager Matt Byatt said the new design is helpful,
considering embedded systems integrators were somewhat limited in their
choices.

“Previously, you would have had to choose between a general-purpose DSP
architecture, which is flexible but under-performs, or a fast single
processor, which is frequently very expensive and has a long development
cycle.”

The OptimoDE tool suite is an interaction between ARM’s DesignDE, DevelopDE and BuildDE applications. DesignDE is an architecture definition creation file; DevelopDE is a profiling and analysis tool that generates micro-code for the architecture you are developing; and BuildDE is an RTL implementation generator.

Byatt said customers include National Semiconductor, Philips Advanced Development Labs, and hearing aid manufacturer Phonak.

ARM is showing off both designs this week as part of the Embedded
Processors Forum.

News Around the Web