Big Blue Takes 5, Advances POWER Line

SAN JOSE, Calif. — IBM Tuesday introduced its POWER5, the company’s next-generation high-end server chip for commercial processing, which allows for simultaneous multi-threading, better power management and virtual partitioning.

The processor will be shipping in mid-2004, but don’t look to pick up a gross of 1,000 at a discount, as Big Blue will only be pre-installing them in iSeries and pSeries server systems and development partners.

The Armonk, N.Y.-based company is presenting detailing its capabilities at the Microprocessor Forum conference here. The POWER5 is expected to go head-to-head with similar RISC chips from Hewlett-Packard and Sun Microsystems.

Based on the previous POWER 4 family the POWER5 is a two-core processor with on- chip memory with just under 2MB of L2 cache and support for DDR 1 and DDR 2 memory.

Whereas previous POWER4’s allowed for scaling up to a 32-way configuration without clustering, IBM says the POWER5 doubles that to 64-physical processors without clustering. The company says the chip’s simultainous multi-threading also makes it look like 128-threaded processor cores. The chip is application compatible with POWER4 and POWER4+ systems but not pin compatible.

“It’s primarily SMP [Symmetric MultiProcessing] configuration that will go in the top to bottom of our systems including clustering,” IBM Systems Group vice president of Technology Development Mark Papermaster told “We started out with a good processor with the POWER4 and its mainframe reliabilities and then packed the POWER5 with a very efficient processing ability to either scaling up or out.”

The processor is pre-configured to run IBM’s UNIX variant AIX, its version of Linux and OS400 for iSeries platforms. Even though Microsoft has released its Server 2003 operating environment, IBM said its customers were not asking for Windows. The company did not immediately disclose the chip’s final debut speeds, Papermaster said the POWER5 would range between 1.6 GHz and 3 GHz over the life of the family.

“Speed is not a factor,” Papermaster said. “What we’ve found is that the main thing is to optimize the silicon investment, If you look at POWER5 the ability to multi-threading, that really allows customers to have flexibility and reliability.”

The design is a result of a close collaboration between IBM Systems Group and IBM Microelectronics technologies. The processor was built on the 130nm process at the company’s plant in East Fishkill, NY. IBM said the next generation POWER5 would be migrating from its 200mm wafers to 300mm using 90nm process technology as early as 2005.

Similar to the POWER4 family, the new chip also takes advantage of features such as Capacity Upgrade on Demand, Logical Partitioning and Chip Kill Memory. The processor also comes with IBM’s Dynamic Power Management, Dynamic Firmware Upgrades, and Dynamic Virtualization. IBM says the virtualization aspects of the chip another characteristic of its e-business On Demand strategy.

For example, the company says as business increases, additional CPUs can be added to absorb the increased transaction volume. The operating system uses the CPUs as a pool of processing resources, all executing simultaneously, either processing data or in an idle loop waiting to do something. However, if one CPU fails, the entire SMP system, or node, is down. Clusters of two or more SMP systems can be used to provide high availability, or fault resilience, in case of failure. If one SMP system fails, the others continue to operate. SMP usage is expected to grow rapidly, and applications are increasingly being designed to take advantage of the SMP architecture.

“Also with the POWER5, the new power management has no performance penalty,” Papermaster said. “We put a set of controls that only burns the part of the chip that it uses.”

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