Big Blue Thinks Small for Transistors

SAN FRANCISCO — Researchers at IBM Monday say they’ve come up with the world’s smallest working silicon transistor, one that may help continue to shrink CMOS devices.

At six nanometers in length, the Armonk, N.Y.-based company said this new transistor is at least 10 times smaller than the state-of-the-art transistors in production today. A nanometer (nm) is one billionth of a meter.

Transistors have been shrinking in size for the past 30 years to keep up with the demand for smaller and more intelligent electronic devices. Scaling the transistors or reducing the gate length (the size of the switch that turns transistors on and off), improves the performance and speed of chips as well as lowers their manufacturing cost and power consumption.

Scientists with IBM Research and IBM Microelectronics at IBM’s research facility in Yorktown Heights, N.Y. made the silicon channel devices and circuits on bonded silicon-on-insulator (SOI) wafers using halo implants and 248nm-wavelength lithography. With more aggressive halo, the IBM team claims it has produced the smallest working Metal Oxide Semiconductor Field Effect Transistor (MOSFET) reported to date, with 4nm silicon body and 6nm gate lengths. A MOSFET is a voltage controlled power device that is capable of handling large electrical current flow.

IBM’s team says their results suggest that aggressive thinning of the SOI layer is a good way to continue shrinking CMOS devices.

“The ability to build working transistors at these dimensions could allow us to put 100 times more transistors into a computer chip than is currently possible,” said Dr. Randy Isaac, vice president of science and technology, IBM Research. “Moreover, this achievement underscores the fundamental challenges of scaling, namely power density, that must be addressed as silicon is pushed to molecular dimensions.”

Intel and Advanced Micro Devices AMD are two other major companies working on shrinking the size of transistors through the use of nanotechnology.

IBM will present details of this research in a paper titled “Extreme Scaling with Ultra-thin Silicon Channel MOSFETs” at the International Electron Devices Meeting (IEDM) being held in San Francisco this week.

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