Chipmaker Takes Next Step in ‘Nano’ Race

Texas Instruments (TI) has become the latest
chipmaker to solidify plans to produce chips that are smaller than
90-nanometers (nm) in size.

The Dallas-based firm said it is currently on track to sample a wireless
65-nm Complementary Metal Oxide Semiconductor (CMOS) processor in the first
quarter of 2005, maintaining its two-year cycle between manufacturing
technology generations. A nanometer is one-billionth of a meter.

TI said the new technology will be used on its
lineup of 4-megabit SRAM memory test arrays, which is
currently in production. The technology is expected to be combined
with TI’s OMAP processors and TCS cellular chipsets in future mobile

“TI’s 65nm CMOS process doubles the transistor density over our qualified
90nm production process and positions us for a leadership role in delivering
the benefits of 65nm to customers early next year,” TI CTO Hans Stork said
in a statement. “Along with the tremendous increase in functionality TI will
offer at 65nm with highly- integrated [system on a chip] designs, we are
taking significant steps to lead the industry in managing the power those
designs consume.”

The sub-90 nanometer level is one of the fastest
emerging areas in the sector as chipmakers look to cram faster processors
into smaller spaces. While the practice is emerging in some microprocessor
circles, it is still considered a new brass ring for mainstream CPUs. TI
rivals IBM , Intel , AMD
and others all have very clear roadmaps for the sub-90nm level mostly in
memory production.

For example, chipmaking giant Intel said its 65-nm technology is on a
fast track to extend its 15 year record of meeting or beating Moore’s Law
and churning out a new process generation every two
years. In fact, it’s been just under a year since Intel said it has achieved
a fully functional SRAMs made with the 90-nm process. Likewise, Motorola
recently said it would produce transistor sizes of 90-nm by mid-2005 and
then switch to 65-nm technology in 2006. IBM has, and is, investing billions
in nano. Its latest chip plant in East Fishkill, N.Y., is expected to cost
$2.5 billion and enable the company to make chips. The company’s efforts
eclipse even the U.S. National Nanotechnology Initiative’s recently endowed
$600 million budget. With the help of Big Blue, AMD said it will plan on
moving to the 90-nm in the first half of 2004 and 65-nm sometime between
late 2005 and early 2006, about the same time the company said it plans on
transferring its wafer production from 200-mm to 300-mm.

TI said its differentiator is its focus on persistent power problems
found in nano-scale chips. For example, for its 65-nm family, TI said it is
saving 1000 times the power of comparable chips by including back-biasing of
SRAM memory blocks, retention circuitry that lets the voltage to drop very
low without requiring a rewrite of the logic, and SmartReflex circuits. The
company’s 65nm process also includes up to 11 layers of copper interconnect
integrated with a low-k dielectric.

The 65nm advances are also a boon to Sun Microsystems, which relies on TI
for its processors. Sun said TI’s sub-90nm plans will be the foundation to
build next generation 64-bit processor designs that support its Throughput
Computing initiative and UltraSPARC roadmap.

TI said it is developing the 65-nm technology for both 200mm and 300mm
wafers and is scheduled to present a technical paper on the 65nm low power
process at the VLSI Symposium in Hawaii in June.

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