A group of chipmakers led by IBM
has stepped up efforts
this week to shrink processors to sizes smaller than the head of a pin.
Samsung Electronics is the latest member to join the development
partnership. The alliance announced Friday plans to create a next-generation chip design platform so fabrication plants can build CMOS
The four companies are working out of IBM’s 300mm Advanced Semiconductor
Technology Center in East Fishkill, New York, and will be able to use what
they develop in their own manufacturing facilities.
In a separate agreement with IBM, Samsung now has the license rights to
90nm CMOS logic technology. South Korea-based Samsung said it plans to add
what it learns with IBM to its System-On-Chip (SOC) product line such as
HD-TVs, DVDPs, and mobile applications.
Samsung has been doing some of its own nanometer-scale developmen
t. Back in September 2003, the company announced its own 70nm 4Gigabit
NAND Flash memory and an 80nm DRAM device. In addition, the company
announced a single chip memory package, called fusion memory, which takes
the multi-chip package and system-in-package concepts one step further to
deliver a single design combining memory and logic.
The sub-90 nanometer level is one of the fastest emerging areas in the
sector as chipmakers look to cram faster processors into smaller spaces.
While the practice is emerging in some microprocessor circles, it has been
somewhat of the new brass ring in mainstream CPUs.
Intel, for example, is looking at releasing Pentium chips based on the
90nm process level by the end of this year with 60nm due out in 2005. Given
Moore’s estimates of 2 or 3 years between generations, 45nm and 30nm
processors should be readily available by 2010.
AMD says it will plan on moving to the 90nm in the first half of 2004 and
65nm sometime between late 2005 and early 2006, about the same time the
company plans on transferring its wafer production from 200mm to 300mm.
IBM has been at the forefront of nanotechnology development, however. Big
Blue’s work with carbon nanotube logic circuits and molecular electronics,
for example, is squarely aimed at maintaining its commercial edge through
the release of more powerful computers five, 10 or 15 years into the future
“If you are in the semi business you need to keep moving along the technology curve.” In-Stat/MDR Steve Cullen, Director & Principal Analyst told internetnews.com. “Some are leaders, some are fast followers, and others deal in mature technologies. IBM has built its business around being a leader, so it needs to be looking five-plus years out and today, that means 45 nm. Intel is also a leader and I’m certain is working on 45nm. But they are large enough (more than 15 percent market share, close to three times that of No. 2 Samsung) that they can afford to go it alone. If you can afford it, alone is better because you never have to compromise your needs to accommodate those of a partner.”
What seems to be different about IBM is the company’s resources. Most
other nanotech initiatives and companies, even the U.S. National
Nanotechnology Initiative’s $600 million budget, pale in comparison. IBM
has, and is, investing billions in nano. Its latest chip plant in East
Fishkill, N.Y. cost $2.5 billion alone.
Back in December, IBM demonstrated “molecular self assembly”, a technique
that uses nanotechnology components to help build smaller and faster
Industry Trend: Think Small
According to a report issued by the International Technology Roadmap for
Semiconductors (ITRS) in January, chipmaking advances such as using
nanotechnology should slow down from its rampant 2-year cycles to a more
manageable three-year ones. Such was the case from the first processors
being built on the 130-nanometer (nm) process in 2002 to 90nm chips coming
“It’s just basically the rate at which the technology is evolving,” ITRS
Vice president for Technology Juri Matisoo told internetnews.com in a
recent interview. “The benefit is that it follows closer to Moore’s Law.
Companies want to work toward making chips smaller because it helps them get
faster, take up less power and cheaper — as much as 25 percent — for the
same functionality. There are fierce competitors pushing the technology and
the one who gets there first with the most products gets the most money.”
The advances also come with their own unique challenges such as leakage
and power dissipation.
“From a point of view of the physics it is possible but going down to the
nano-level and making these things by the billions is a huge challenge for
designers,” Matisoo said. “One of the biggest problems as you scale down and
the density per square micron is getting the power in and getting the heat
out. And then there are issues with the fabrication. How do you test the
chips to make sure that it does what you designed it to do.
A new problem now facing chipmakers is the cost of actually building and
bringing one to market. The industry trend to move to 90nm comes with an
estimated $30 million price tag.
During its yearly forecast, Semiconductor Industry Association (SIA)
officials pointed to rising chip development costs with each new process
node. For example, if a company is spending 20 percent on research and
development, the revenue target of that company should be
about $150 million. Compound that with a company that has at least 10
percent market share with a $1.5 billion in revenues and the justification of ASIC/ASSP development requires approximately $1 billion in R&D.
That cost, according to Matisoo, may be mitigated in building larger sized wafers, which would fit more chips on it per-square-millimeter, but that may take another eight
years to come to fruition. The industry currently uses 200mm and 300mm
wafers that cost about the same to produce.
“How much a chip costs, depends on how many you can get on a wafer,”
Matisoo said. “The rule of thumb is that an average wafer costs between
$1,000 to $2000. There is a roadmap to increase that wafer size to 400mm
starting around 2012, but that is a ways off.”