IBM Breeds Cross-Foundry Design Program

In its quest to make smaller, more cost-effective chips IBM
said it has chartered a cross-foundry design “enablement” program this week
with Singapore-based Chartered Semiconductor Manufacturing.

The Armonk, N.Y.-based computer maker said it wants to “significantly
increase the pool of available IP and design solutions for 90-nanometer
chips and beyond,” which continues to be one of the
fastest emerging areas in the System-on-Chip (SoC) design sector.

The partnership is a shot across the bow of Taiwan-based semiconductor
foundries like TSMC and UMC , which are now expected to
offer similar plans in order to keep up.

“We have the most advanced and production-worthy common 90-nm process
available today. The next step is to help our customers rapidly design and
implement new products based on the technology,” Bernie Meyerson, vice
president and chief technologist, IBM Systems and Technology Group said in a

The problem facing chipmakers is the cost of actually building and
bringing smaller chips to market. The industry trend to move to 90nm comes
with an estimated $30 million price tag, according to the 2003 edition of the International Technology Roadmap for
Semiconductors (ITRS).

Industry leaders say that cost may be mitigated in
building larger sized wafers, which would fit more chips on it
per-square-millimeter, but that may take another eight years to come to
fruition. The industry currently uses 200mm and 300mm wafers that cost about
the same to produce.

“How much a chip costs, depends on how many you can get on a wafer,”
Semiconductor Industry Association vice president for Technology Juri
Matisoo told in a January interview. “The rule of
thumb is that an average wafer costs between $1,000 to $2000. There is a
roadmap to increase that wafer size to 400mm starting around 2012, but that
is a ways off.”

IBM said it is working with Chartered to expand the program for
design technology and service providers with the promise of
“pre-qualification” for the joint IBM-Chartered 90-nm silicon process

The companies say the first key milestone is shared library
support with companies that compile baseline libraries. Big Blue has already
signed up two design library partners: Silicon Valley-based Artisan
Components and Virage Logic .

Artisan said its front-end views for Advantage Memory Generators, SAGE-X
Standard Cell and general-purpose I/O libraries are expected to be available
in the second quarter of 2004 for the Low-K process. Complete views are
expected to be available by the third quarter of 2004.

Likewise, Virage said
its Technology-Optimized Platform and ASAP Logic Metal Programmable Cell
Libraries would be available on the Chartered and IBM joint 90-nm
manufacturing process platform starting in the second quarter of 2004.

IBM has been at the forefront of nanotechnology development. The
company’s work with carbon nanotube logic circuits and molecular
electronics, for example, is squarely aimed at maintaining its commercial
edge through the release of more powerful computers five, 10 or 15 years
into the future and beyond.

What’s different about IBM is the company’s resources. Most other
nanotech initiatives and companies, even the U.S. National Nanotechnology
Initiative’s $600 million budget, pale in comparison.

IBM has and is investing billions in nano. Its latest chip plant in East Fishkill, N.Y.,
cost $2.5 billion.

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