IBM Sweet on PSL Chip Design Language

A new computer language was approved as an official industry standard Thursday; one designed specifically to improve the accuracy of the semiconductor design process.

Standards organization, Accellera EDA, gave the green light to the Property Specification Language (PSL) version 1.01 to “advance assertion-based verification in simulation and formal verification,” the two techniques currently used in testing chip designs.

Based on IBM’s Sugar language (currently in version 2.0), PSL is used for the formal specification of hardware and by engineers to specify the functional properties of logic designs. The properties, in turn, serve as input to property-checking tools, which Accellera says are key to modern-day functional verification. The standards body is a consortium of more than 40 individuals representing over 20 companies.

The group says it was prompted to look at standardizing the language as more and more EDA companies began supporting verification tools driven by PSL. For example, Armonk, N.Y.-based IBM, provides an open source Sugar parser to tool developers. Accellera developed the complete language reference manual (LRM) for PSL.

“The approval of Accellera’s PSL standard, based on IBM’s technology contribution, is a significant milestone for Accellera and improves the productivity of designers doing system-level design and verification,” Accellera chairman Dennis Brophy said in a statement. “Accellera members and the PSL technical team have done an outstanding job to get PSL ready for deployment.”

To accelerate the adoption of PSL, 15 companies have combined forces to form the PSL/Sugar Consortium. The purpose of this organization is to drive the development of tools and methodologies that will support the new standard.

The new organization held its first meeting at the Design Automation Conference (DAC) in Anaheim California this week. The meeting attracted a record number of attendees and included presentations from representative of semiconductor companies who presented verification methodologies based on PSL.

“The new standard will help design and verification engineers, as well as tool developers, meet the demands of the chip design and EDA industries and provide competitive advantages to their customers,” said Dr. Michael Rodeh, Director of Haifa Research Lab where the Sugar language was conceived. “The ratification of PSL by the board of Accellera will expedite the dissemination of advanced specification and verification methodologies.”

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