IBM’s 3D IC: No Funny Glasses Needed

Laying claim to an important step along the path to creating mightier integrated circuits (ICs), IBM Monday said it has crafted a new technique for building three-dimensional ICs that will help increase chip performance, functionality and density.

Researchers at IBM’s Research Division lab in Yorktown Heights, N.Y. explained that current microprocessors are two-dimensional, existing in one plane with a multi-layer system of wires used to connect different parts.

IBM said the last dimension bolsters performance and increases density by reducing the length of the wires that connect transistors and increasing bandwidth between logic and memory; facilitating the integration of heterogeneous materials, devices, and signals, such as placing electrical and optical devices on different levels of the same chip; and allowing more transistors to reside on a chip.

IBM explained that although 3D chips are attractive to many companies for their sheer speed, mainstream adoption has been slug-like because the fabrication process has proven difficult.

The Armonk, N.Y.-based technology concern said many research groups take the “bottom-up” approach to building 3D ICs, in which each device layer is fabricated sequentially, starting with the bottom-most layer.

“Unfortunately, the quality of each new layer of silicon that is grown or deposited on top of the existing devices is typically worse than the original silicon layer,” IBM explained in a company statement. “Also, many of the processes required for building devices on each subsequent layer can degrade the devices below, making this approach unsuitable for high performance technology.”

IBM said its new technique should remedy this dilemma. The firm’s method for building 3D ICs based on the layer transfer of completed circuits involves transferring functional circuits from one wafer to another and connecting the multiple layers electrically to form the 3D chip. This transfer is what the company calls a “wafer-level bonding approach.”

Ron Guttman, a professor who teaches at the Rensselaer Polytechnic University and who spearheads a team researching 3D ICs for the Interconnect Focus Center, said that although the products are not there yet because of the complicated fabrication process, the research is important.

“Ten years ago, companies were principally making ICs smaller to increase performance. Then, as interconnect issues became the problem, firms such as IBM began making copper chips [instead of silicon] with low K dialetric material,” Guttman told “As one continues to make those material-related changes, one runs out of steam. Since there is not much you can do for interconnect scaling, the new 3D layering is quite a paradigm shift. Rather than making [chips] bigger, and then putting them in packages where they’re assembled and analagous to suburban sprawl, 3D technology has active device layers at more than one level, which is very significant in the road to this technological change

The 3D process is cooler, too, extending the chip’s life. The layer transfer technique uses low process temperatures and mechanical stresses to preserve the devices on the silicon wafers. IBM employs 130 nm silicon-on-insulator (SOI) devices with copper metallization and “low-k” dielectric insulators to withstand the transfer processes.

Big Blue researchers will further detail the technique in a paper at the International Electron Devices Meeting (IEDM) held in San Francisco, Dec. 9-11, 2002.

This article originally appeared on

News Around the Web