Intel Expanding Moore’s Law with Nano

SAN JOSE, Calif. — When Intel founder Gordon Moore postulated the size and speed of future chips, the thinking was that things would eventually slow down because of the limits of silicon.

Now the Santa Clara, Calif.-based chip making giant is pushing that end point with its exploration into nanotechnology .

But company CTO Pat Gelsinger and Intel Senior Vice President Sunlin Chou Thursday reminded developers that silicon technologies are still the building blocks to getting smaller and more efficient devices.

“We will continue to drive Moore’s Law by building more capabilities into our silicon through advanced research and investment in nanotechnology,” said Chou. “WE have been producing CPUs using sub-100 nanometer transistors for the last two years. Our research goes well beyond next year’s 90 nanometer technology to evaluate longer term options that will continue to renew silicon technology and extend its scalability into the next decade.”

Some of the technologies Intel is pursuing include the development of “silicon radios” based on the company’s low-power CMOS manufacturing process. Over the next few years, the company said these radios will be integrated into future Intel chips, so any device powered by one of those chips would have wireless radio communication capabilities.

In addition, Gelsinger demonstrated a tunable laser using silicon photonics and said Intel’s research is on track to apply Moore’s Law toward building highly integrated components that marry digital functionality and silicon-based opto-electronic devices on a single chip. The goal is to lower the cost of optical networks by mixing the component technologies into low-cost silicon building blocks.

Another of Intel’s research projects on Terahertz transistors (high-speed transistors that Intel plans to put into production around 2007) focuses on experimental high-performance, non-planar triple-gate CMOS transistors (called Tri-Gate transistors).

This type of transistor moves away from the current “planar” (flat) design, and instead is designed using a three-dimensional architecture, which increases the surface area of the transistor gate, thus increasing performance and enabling higher speed processors.

Intel said such transistors would require further improvement before going into production.

Part of the difficulty is that the lithography methods used in making the blocks smaller has gotten too broad to take the next step.

“It’s like trying to use a wide brush to paint the thinner and thinner lines. Eventually, it becomes impractical,” said Chou.

Intel said it is getting around that obstacle by working with Extreme Ultraviolet (EUV) lithography, new transistor gate dielectrics and transistor structures. Currently, EUV lithography is in commercialization phase. The company said it expects to hit the 13nm mark by 2007. Intel is helped by its participation in the EUV LLC consortium, an industry-government collaboration that includes three U.S. Department of Energy national laboratories and companies like Intel, Motorola, Advanced Micro Devices, Micron Technology, German-based Infineon Technologies and IBM.

The work with EVU and transistors will be applied to other innovations such as strained silicon and put into production on Intel’s 90nm manufacturing process next year.

As for Intel’s long-term nanotechnology plans, the company would not speculate between standing completely behind either carbon nanotubes or nanowires. Both technologies are aggressively being researched with expected industry rollout by 2010. Intel said it would most likely follow the one that best stands up to mass production

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