Intel Makes Nano Leap

Intel Corp. on Tuesday announced plans to use a technology that stretches
the atoms apart in a silicon wafer, a process that mass-produces the world’s
smallest transistors.

The Santa Clara, Calif., chip maker’s big leap into the nanotechnology era
extends on the “strained silicon” technique first adopted by competitor IBM
Corp but Intel would be the first to use it in large scale

By stretching the atoms, Intel said the new technology
would allow electrical current to flow faster, boosting computing
performance and, more importantly, reduce chip-making costs in a tough
market for the semiconductor group.

While chip makers are constantly tinkering at the sub-micron level and
shrinking the chips and transistors, Intel said chips make on the 90 nm
process would also include new insulation techniques and internal components
would be tinier. The new chip, dubbed ‘Prescott’, will be available in late
2003, Intel said.

Intel said the new process, which is part of plans to spend $12.5 billion
over two years on chip-making technologies, could actually create
transistors whose key features are just 50 nanometers. The latest advances
are aimed at the nanotechnology era, where
chip-making science is geared towards controlling individual atoms and
molecules that are thousands of times smaller than current technologies

Intel, one of a handful of companies in the semiconductor group with the
financial might to go it alone on new chip-making technologies, also
announced plans to move to 12-inch silicon wafers, up from the current
standard of eight inches, at two factories in New Mexico and Oregon. The
move would cut production costs by at least one-third per chip.

Intel said the Oregon foundry would manufacture the chips of the 90nm
process in the interim while the company’s facilities in New Mexico and
Ireland would handle the mass production of the new chips.

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