Monday turned the spotlight on a key component of its new Yellowstone signaling technology, a new circuit
technology designed to aid memory system designers in developing simpler and more compact memory layouts.
Dubbed FlexPhase because it enables flexible phase — allowing precise on-chip alignment of data with clock in order to eliminate
the need for PCB trace length matching and strict PCB timing constraints — Rambus said the technology will allow memory system
designers to circumvent matching adjacent data traces to an associated clock or strobe.
According to the company, the technology differs from traditional serial link approaches because it does not use an embedded clock,
allowing chip connections to avoid the added latency and 20 percent bandwidth penalty associated with eight- to 10-bit encoding.
Rambus also said FlexPhase enables in-system timing characterization and self-test functionality accurate to within 2.5ps.
FlexPhase rounds out the technologies that make up Yellowstone, which also include Differential Rambus Signaling Levels (DRSL) and
Octal Date Rate (ODR). Together, the technologies give Yellowstone data rates from 3.2 GHz to 6.4 GHz, resulting in memory
bandwidths of 10 to 100 GB/s, according to the company. The Yellowstone technology is intended to dramatically improve performance
in memory signaling while lowering system cost through pin-count reduction and the elimination of external termination resistors.
Yellowstone, which Rambus demonstrated at the Rambus Developer Forum in Japan on July 2 and 3, is available for licensing now. The
company is already working with customers and expects to see systems incorporating the technology — including video game consoles
and systems for networking and PC graphics — by 2004.