Transmeta will add a new antivirus technology
standard to its next round of low-power chips, the company said Monday.
The Santa Clara, Calif.-based concern said it has agreed to work with Microsoft Microsoft has been planning to ship the software support technologies Transmeta said its hardware is scheduled to ship NX uses x86-based architecture CPUs to mark all memory While buffer overruns also plague Unix and Linux environments, Transmeta “Software programs alone are weak. They don’t check every case as they The company was able to tweak its new Efficeon chips with NX technology Microsoft and Transmeta have a longstanding relationship. For example, As for Efficeon’s future, Transmeta said it does expect a beta of the x86 However, unlike roadmaps from Intel and AMD, Transmeta has expressed no “Our technology is different. We don’t have some of the same heat
on the software giant’s “No Execute” (commonly known as “NX”) technology, a security feature that is a combination of hardware and Microsoft’s Execution
Protection software.
The companies said the combination reduces memory buffer
overruns that many hackers exploit to insert malicious code into Windows
such as the MS Blaster, Code Red, and recent Sasser worms.
as part of its forthcoming Windows XP Service Pack 2 (SP2) and has worked
with other chipmakers on support for the new security features. Intel said it would include NX in its Pentium 4 “Prescott” later
this year. AMD already has the technology as a part of its
Athlon 64 and Opteron processors.
with NX in mid-year 2004 with its new TM8000-series “Efficeon” processors.
locations in an application as non-executable unless the location explicitly
contains executable code. This way, when an attacking worm or virus inserts
program code into a portion of memory marked for data only, it cannot be
run.
said it is working with Microsoft first. The company that used to employ
Linux founder Linus Torvalds said for Linux to take advantage of NX would
require a kernel upgrade.
should,” John Heinlein, Transmeta director of strategic partner initiatives,
told internetnews.com. “If you take a data region and store more data
than you are supposed to… you can cause some code to execute. What this
innovation does is provides hardware support to mark regions as not
executable — stopping these attacks.”
without changes in silicon in part because of its proprietary Code Morphing
Software, which translates inbound x86 instructions into the Efficeon’s
native Very Long Instruction Word (VLIW) instructions at run-time. Heinlein
said.
the Redmond, Wash.-based software vendor handpicked
Transmeta as its reference design partner to help develop the next
generation of its Smart Displays (code-named Mira).
compatible chip to debut on or before the Windows SP2 release. The processor
for mobile, wireless, and embedded devices should build on its past
architecture including three new high performance bus interfaces: an on-chip
HyperTransport bus interface for increased input/output efficiency, an
on-chip Double Data Rate (DDR) SDRAM memory interface for increased
throughput, and an on-chip AGP graphics.
plans to adopt either a 64-bit architecture or a multi-threaded strategy.
problems that the others have,” Heinlein said.
