TSMC Touts New Chip Making Technology

The world’s largest chip foundry-for-hire said it is gearing up to release new products this year based on 65-nanometer (nm) process technology.

Taiwan Semiconductor Manufacturing Company said its
new Nexsys technology for system-on-chip (SoC) design is in place, which
will let designers build logic devices with twice the density of current
90-nm technology. The shift also means more information can be
compacted in a smaller space — the equivalent of more than 750 billion
transistors on a single 12-inch wafer.

SoC design is preferred by many of TSMC’s customers because it
includes on-chip memory (RAM and ROM), the microprocessor, peripheral
interfaces, I/O logic control, data converters and other components.
Processors using SoC are used in digital cameras, cellular phones, set-top boxes and PDAs.

The fab expects the first 65-nm wafers to come out in
December. The new 65-nm process will be used initially at TSMC’s
300mm manufacturing facilities.

“TSMC is already the foundry leader in 0.13-micron-and-below
manufacturing technologies, with volumes and revenues that are multiples
ahead of our nearest competitors,” Kenneth Kin, a senior vice president
at TSMC, said in a statement. “The new 65-nm Nexsys technology represents
yet another leadership point from which the industry can rapidly
accelerate the pace of innovation.”

TSMC’s first 65-nm silicon was a fully functional SRAM
built back in April 2004 that featured more than 100 million
transistors. Since then, some customers including Altera have designed their own.

In response to customer demand, TSMC said its first 65-nm Nexsys
technology will be designed specifically for low-power devices. A
high-speed version will be available in 2006, followed later in the year
by a general-purpose 65-nm process. A version that uses silicon on
insulator (SOI) technology and an ultra-high-speed version will be
introduced in 2007. TSMC said it would include logic and mixed-signal
options for all versions, with embedded memory available in each.

The new technology features a minimum number of process changes, such
as strained silicon and a new nickel silicide. The foundry said its
65-nm Nexsys technology is the third-generation TSMC process to use
low-k dielectrics and the fourth generation to use copper interconnects.

From a power and performance perspective, TSMC said its 65-nm Nexsys
technology has a 50 percent speed gain over its 90-nm designs in general
purpose uses and a 20 percent standby power reduction.

Another feature being added to the 65-nm designs will be an
electrical fuse technology to allow for improved identification and
configuration of devices.

Early design rules and simulation models for the new technology are
already being tested, TSMC said. The company expects its libraries will
be available in the fourth quarter of 2005, and third party library and
IP developers are fast at work developing additional offerings.

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